Abstract
Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DDMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time stacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our call chain balancing (CCB) algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of run-time memory in the target code.
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Aho, A.V., Sethi, R., Ullman, J.D.: Compilers -Principles, Techniques, and Tools. Addison-Wesley Publishing Company, Reading (1986)
Cho, J., Paek, Y., Whalley, D.: Fast Memory Bank Assignment for Fixed-Point Digital Processors. ACM Transactions on Design Automation of Electronic Systems 9(1), 52–74 (2004)
Motorola Inc. DSP56301 User’s Manual (1999), http://www.motorola-dsp.com
Lee, C., Potkonjak, M., Mangione-Smith, W.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In: Proceedings of the 30th Annaul IEEE/ACM Internation Symposium on Microarchitecture, pp. 330–335 (1997)
Leupers, R., Kotte, D.: Variable partitioning for dual memory bank DSPs. In: Proceedings of the IEEE International Conference on Acoustics Speech and Signal Processing, pp. 1121–1124 (2001)
Liem, C.: Retargetable Compilers for Embedded Core Processors. Kluwer Academic Publishers, Dordrecht (1997)
Saghir, M.A.R., Chow, P., Lee, C.G.: Exploiting Dual Data-Memory Banks in Digital Signal Processors. ACM SIGOPS Operating Systems, 234–243 (1996)
Sudarsanam, A., Malik, S.: Simultaneous Reference Allocation in Code Generation for Dual Data Memory Bank ASIPs. ACM Transactions on Design Automation of Electronic Systems 5(2), 242–264 (2000)
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© 2006 Springer-Verlag Berlin Heidelberg
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Cho, J., Paek, Y. (2006). Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm. In: Zhou, X., et al. Emerging Directions in Embedded and Ubiquitous Computing. EUC 2006. Lecture Notes in Computer Science, vol 4097. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11807964_78
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DOI: https://doi.org/10.1007/11807964_78
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36850-2
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