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Gopal Raut
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2020 – today
- 2024
- [j14]Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar:
QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit. IEEE Access 12: 43600-43614 (2024) - [j13]Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma:
In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst. Signal Process. 43(1): 646-660 (2024) - [j12]Sudheer Vishwakarma, Gopal Raut, Sonu Jaiswal, Santosh Kumar Vishvakarma, Dhruva Ghai:
A Precision-Aware Neuron Engine for DNN Accelerators. SN Comput. Sci. 5(5): 494 (2024) - [c9]Gopal Raut, Pranose J. Edavoor, David Selvakumar, Ritambhara Thakur:
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators. ISQED 2024: 1-8 - [i1]Sonu Kumar, Komal Gupta, Gopal Raut, Mukul Lokhande, Santosh Kumar Vishvakarma:
HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator. CoRR abs/2409.04976 (2024) - 2023
- [j11]Sumiran Mehra, Gopal Raut, Ribhu Das Purkayastha, Santosh Kumar Vishvakarma, Anton Biasizzo:
An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning. IEEE Access 11: 34912-34924 (2023) - [j10]Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma:
Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. Circuits Syst. Signal Process. 42(10): 6089-6115 (2023) - [j9]Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma:
Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs. Circuits Syst. Signal Process. 42(12): 7596-7614 (2023) - [j8]Gopal Raut, Saurabh Karkun, Santosh Kumar Vishvakarma:
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(3): 39:1-39:32 (2023) - [c8]Sudheer Vishwakarma, Gopal Raut, Narendra Singh Dhakad, Santosh Kumar Vishvakarma, Dhruva Ghai:
A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators. IFIPIoT (1) 2023: 433-441 - [c7]Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut:
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. VLSID 2023: 252-257 - 2022
- [j7]Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma:
BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator. Circuits Syst. Signal Process. 41(4): 2045-2060 (2022) - [j6]Gopal Raut, Anton Biasizzo, Narendra Singh Dhakad, Neha Gupta, Gregor Papa, Santosh Kumar Vishvakarma:
Data multiplexed and hardware reused architecture for deep neural network accelerator. Neurocomputing 486: 147-159 (2022) - [j5]Gunjan Rajput, Shashank Agrawal, Gopal Raut, Santosh Kumar Vishvakarma:
An accurate and noninvasive skin cancer screening based on imaging technique. Int. J. Imaging Syst. Technol. 32(1): 354-368 (2022) - [c6]Varun Bhatnagar, Gopal Raut, Santosh Kumar Vishvakarma:
Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array. ACM Great Lakes Symposium on VLSI 2022: 199-202 - [c5]Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu:
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI 2022: 308-313 - 2021
- [j4]Gunjan Rajput, Gopal Raut, Mahesh Chandra, Santosh Kumar Vishvakarma:
VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators. Microprocess. Microsystems 84: 104270 (2021) - [j3]Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar:
RECON: Resource-Efficient CORDIC-Based Neuron Architecture. IEEE Open J. Circuits Syst. 2: 170-181 (2021) - [j2]Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar:
Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture". IEEE Open J. Circuits Syst. 2: 292 (2021) - 2020
- [j1]Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, Santosh Kumar Vishvakarma:
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. Circuits Syst. Signal Process. 39(9): 4681-4694 (2020) - [c4]Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar:
A CORDIC Based Configurable Activation Function for ANN Applications. ISVLSI 2020: 78-83
2010 – 2019
- 2019
- [c3]Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma:
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. VDAT 2019: 321-333 - [c2]Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
An Ultra Low Power AES Architecture for IoT. VDAT 2019: 334-344 - [c1]Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. VDAT 2019: 655-663
Coauthor Index
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last updated on 2024-10-10 22:19 CEST by the dblp team
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