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ORCIDChe-Fu Liang
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- Liangfu Chen (aka: Liang-Fu Chen)
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2010 – 2019
- 2015
[c8]Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang:
A 1V fractional-N PLL with nonlinearity-insensitive modulator. A-SSCC 2015: 1-4- [c7]Che-Fu Liang, Ping-Ying Wang:
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. ISSCC 2015: 1-3 - 2014
- [c6]Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang:
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. ISSCC 2014: 270-271 - 2013
- [c5]Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn:
A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation. ISSCC 2013: 416-417 - 2011
- [c4]Che-Fu Liang, Keng-Jan Hsiao:
An injection-locked ring PLL with self-aligned injection window. ISSCC 2011: 90-92
2000 – 2009
- 2009
- [j7]Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu:
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 107-111 (2009) - 2008
- [j6]Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu:
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems. IEEE J. Solid State Circuits 43(2): 390-398 (2008) - [j5]Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. IEEE J. Solid State Circuits 43(5): 1217-1226 (2008) - [j4]Che-Fu Liang, Hong-Lin Chu
, Shen-Iuan Liu:
10-Gb/s Inductorless CDRs With Digital Frequency Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(9): 2514-2524 (2008) - [c3]Che-Fu Liang, Shen-Iuan Liu:
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells. ISSCC 2008: 224-225 - 2007
- [j3]Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A Multi-Band Burst-Mode Clock and Data Recovery Circuit. IEICE Trans. Electron. 90-C(4): 802-810 (2007) - [j2]Che-Fu Liang, Hsin-Hua Chen, Shen-Iuan Liu:
Spur-Suppression Techniques for Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs 54-II(8): 653-657 (2007) - 2006
- [j1]Che-Fu Liang, Shih-Tsai Liu, Shen-Iuan Liu:
A Calibrated Pulse Generator for Impulse-Radio UWB Applications. IEEE J. Solid State Circuits 41(11): 2401-2407 (2006) - [c2]Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS. CICC 2006: 599-602 - [c1]Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma:
A 14-band Frequency Synthesizer for MB-OFDM UWB Application. ISSCC 2006: 428-437
Coauthor Index
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