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ORCIDA. Neslin Ismailoglu
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2000 – 2009
- 2008
[b1]Ayse Neslin Ismailoglu:
Asynchronous design of systolic array architectures in cmos ; cmos devrelerle asenkron sistolik dizi mimarisi tasarımı. Middle East Technical University, Çankaya, Ankara, Turkey, 2008- [c9]A. Neslin Ismailoglu, Murat Askar
:
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. DSD 2008: 566-571 - [c8]Ayse Neslin Ismailoglu, Murat Askar:
Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic. ICECS 2008: 1063-1066 - 2007
- [c7]A. Neslin Ismailoglu, Murat Askar:
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. ISCAS 2007: 3259-3262 - 2006
- [c6]A. Neslin Ismailoglu, Oguz Benderli, Soner Yesil, Refik Sever, Burak Okcan, O. Sengul, Rusen Öktem:
GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small Satellites. AHS 2006: 351-358 - 2005
- [c5]Rusen Öktem, Oguz Benderli, A. Neslin Ismailoglu:
Improving compression ratio for satellite transmission by use of cloud extraction. EUSIPCO 2005: 1-4 - 2004
- [c4]Refik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, Burak Okcan:
A High Speed FPGA Implementation of the Rijndael Algorithm. DSD 2004: 358-362 - [c3]Refik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar:
A high speed ASIC implementation of the Rijndael algorithm. ISCAS (2) 2004: 541-544 - [c2]Soner Yesil, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar:
Two fast RSA implementations using high-radix montgomery algorithm. ISCAS (2) 2004: 557-560 - 2003
- [c1]Oguz Benderli, Yusuf Çagatay Tekmen, A. Neslin Ismailoglu:
A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. DSD 2003: 384-391
Coauthor Index
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