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ORCIDIntegration, Volume 39
Volume 39, Number 1, September 2005
- Grigoris Dimitroulakos, Michalis D. Galanis, Athanasios Milidonis, Constantinos E. Goutis:
A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000. 1-11 - Scott C. Smith:
Development of a large word-width high-speed asynchronous multiply and accumulate unit. 12-28 - Nabil Abu-Khader, Pepe Siy:
Systolic product-sum circuit for GF((22)m) using neuron MOSFETs. 29-47 - Pieter Rombouts, Ludo Weyten:
A versatile Nyquist-rate A/D converter with 16-18 bit performance for sensor readout applications. 48-61
Volume 39, Number 2, March 2006
- Kaushik Roy:
Guest Editorial. 63 - Bipul Chandra Paul, Amit Agarwal, Kaushik Roy:
Low-power design techniques for scaled technologies. 64-89 - Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara
:
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. 90-112 - David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris:
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. 113-130 - Matthias Müller, Sven Simon, Holger Gryska, Andreas Wortmann, Steffen Buch:
Low power synthesizable register files for processor and IP cores. 131-155
Volume 39, Number 3, June 2006
- Jihyun Lee, Yong-Bin Kim:
ASLIC: A low power CMOS analog circuit design automation. 157-181 - Victor R. L. Shen:
A PN-based approach to the high-level synthesis of digital systems. 182-204 - Jian-Nong Tong, Xue-Cheng Zou, Xu-Bang Shen:
Simulation for a novel vertical SOI configuration. 205-210 - Mohamed Raseen, P. W. Chandana Prasad, Ali Assi:
An efficient estimation of the ROBDD's complexity. 211-228 - Nabil Abu-Khader, Pepe Siy:
Systolic Galois field exponentiation in a multiple-valued logic technique. 229-251 - Rezaul Haque, Andrzej Sendrowski, Bob Baltar, Saad Monasa:
Design of a high-speed, low-noise CMOS data output buffer. 252-266 - Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri:
Hierarchical constraint transformation based on genetic optimization for analog system synthesis. 267-290 - Joanna C. K. Lai, Waleed H. Abdulla, Stephan Hussmann:
Hardware implementation of a sub-pixel algorithm for real-time saw blade deflection monitoring. 291-309
Volume 39, Number 4, July 2006
- Lei Yang, Chuanjin Richard Shi:
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. 311-339 - Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia:
On whitespace and stability in physical synthesis. 340-362 - Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh:
A parameterized graph-based framework for high-level test synthesis. 363-381 - Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon:
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. 382-406 - Anu Gupta, Bipin Kulkarni:
Automation of clock distribution network design for digital integrated circuits using divide and conquer technique. 407-419 - Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
Multilevel routing with jumper insertion for antenna avoidance. 420-432 - Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine:
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. 433-456 - Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. 457-473 - Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu:
Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398]. 474-476
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