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ORCID28th PATMOS 2018: Platja d'Aro, Spain
- 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018. IEEE 2018, ISBN 978-1-5386-6365-3
- Lembit Jurimagi
, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin:
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. 1-6 - Roberto Sierra, Carlos Carreras, Gabriel Caffarena:
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. 7-12 - Hernan Aparicio, Pablo Ituero:
A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations. 13-18 - David Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez:
VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC. 19-22 - Amal Ben Ameur, Michel Auguin, François Verdier, Valerio Frascolla:
Mobile Terminals System-Level Memory Exploratio for Power and Performance Optimization. 23-28 - Guillem Martinez de Arriba, Ertugrul Coskuner, Joan J. Garcia-Garcia:
Enhanced RF Harvesting System by the Utilization of Resonant Cavities. 29-31 - Thomas Goldbrunner, Thomas Wild, Andreas Herkersdorf:
Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models. 32-38 - Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications. 39-45 - Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey:
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. 46-53 - P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini:
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. 54-61 - Asghar Bahramali, Marisa López-Vallejo:
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications. 62-67 - Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Denis Flandre, David Bol:
A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. 68-75 - Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski:
A Reliable PUF in a Dual Function SRAM. 76-81 - Enrique Barajas, Xavier Aragonès, Diego Mateo, Francesc Moll, Antonio Rubio, Javier Martín-Martínez, Rosana Rodríguez, Marc Porti, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology. 82-87 - Rida Kheirallah, Jean-Marc Gallière, Nadine Azémard, Gilles R. Ducharme:
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. 88-91 - Filip Segmanovic, Frederic Roger, Gerald Meinhard, Ingrid Jonak-Auer, Tomislav Suligoj:
Optical and Electrical Simulations of Radiation-Hard Photodiode in 0.35μM High-Voltage CMOS Technology. 92-96 - Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos:
UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. 97-102 - Julián Caba, Fernando Rincón, Julio Dondo, Jesús Barba, Manuel J. Abaldea, Juan Carlos López:
Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLS. 103-110 - Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design. 111-117 - M. Pilar Garde, Antonio J. López-Martín, Daniel Orradre, Jaime Ramírez-Angulo:
Ultra-Low Power Subthreshold Quasi Floating Gate CMOS Logic Family for Energy Harvesting. 118-122 - Guillaume Patrigeon, Pascal Benoit, Lionel Torres:
FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC. 123-128 - Andres Amaya, Luis E. Rueda G., Elkim Roa:
A Multi-Level Power-on Reset for Fine-Grained Power Management. 129-132 - Erik S. Skibinsky-Gitlin, Miquel L. Alomar, Eugeni Isern, Miquel Roca, Vincent Canals, Josep L. Rosselló:
Reservoir Computing Hardware for Time Series Forecasting. 133-139 - A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability. 140-146 - Moisés Herrera, Tingyu Wang, Peter A. Beerel:
Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415. 147-154 - Yi Zhao, Cong Hao, Takeshi Yoshimura:
TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing. 155-162 - Erica Tena-Sánchez, Antonio J. Acosta:
Effect of Temperature Variation in Experimental DPA and DEMA Attacks. 163-168 - Sotirios K. Goudos, Nikolaos Karagiorgos, Maria Ntogramatzi, Ioannis Messaris, Spyridon Nikolaidis:
Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates. 169-176 - Roberto Blanco, Pedro Malagón, Juan J. Cilla, José Manuel Moya:
Multiclass Network Attack Classifier Using CNN Tuned with Genetic Algorithms. 177-182 - Vassilis Paliouras, Konstantina Karagianni, Yann Oster:
Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines. 183-190 - Ibrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski:
Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network. 191-197 - Ali Aalsaud, Haider Alrudainy, Rishad A. Shafik, Fei Xia, Alex Yakovlev:
MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems. 198-205 - Ali Aalsaud, Ashur Rafiev, Fei Xia, Rishad A. Shafik, Alex Yakovlev:
Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems. 206-213 - Lennart Bamberg, Alberto García Ortiz:
Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration. 214-221 - Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. 222-228 - Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris:
Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs. 229-236 - Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. 237-242 - Ruzica Jevtic, Marko Ylitolva, Lauri Koskinen:
Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices. 243-247 - Thomas Vandenabeele, Roel Uytterhoeven, Wim Dehaene, Nele Mentens:
A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes. 248-253 - Konstantinos Oikonomou, Orestis Theodorakopoulos, Georgios Keramidas, Georgios Theodoridis:
Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD Displays. 254-260
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