Paper 2024/984

Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation (Extended Version)

Aneesh Kandi, Indian Institute of Technology Madras
Anubhab Baksi, Nanyang Technological University
Peizhou Gan, Nanyang Technological University
Sylvain Guilley, Télécom ParisTech, Secure-IC, Cesson-Sévigné, France
Tomáš Gerlich, Brno University of Technology
Jakub Breier, TTControl GmbH, Vienna, Austria
Anupam Chattopadhyay, Nanyang Technological University
Ritu Ranjan Shrivastwa, Télécom ParisTech, Secure-IC, Cesson-Sévigné, France
Zdeněk Martinásek, Brno University of Technology
Shivam Bhasin, Nanyang Technological University
Abstract

In this work, we present various hardware implementations for the lightweight cipher ASCON, which was recently selected as the winner of the NIST organized Lightweight Cryptography (LWC) competition. We cover encryption + tag generation and decryption + tag verification for the ASCON AEAD and also the ASCON hash function. On top of the usual (unprotected) implementation, we present side-channel protection (threshold countermeasure) and triplication/majority-based fault protection. To the best of our knowledge, this is the first protected hardware implementation of ASCON with respect to side-channel and fault inject protection. The side-channel and fault protections work orthogonal to each other (i.e., either one can be turned on/off without affecting the other). We present ASIC and FPGA benchmarks for all our implementations (hash and AEAD) with/without countermeasures for varying input sizes.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. Major revision. IEEE Computer Society Annual Symposium on VLSI 2024 (ISVLSI 2024)
Keywords
ASCONHardware ImplementationSide-Channel AttackThreshold ImplementationFault AttackCountermeasure
Contact author(s)
aneeshkandi @ gmail com
anubhab baksi @ ntu edu sg
peizhou gan @ ntu edu sg
sylvain guilley @ telecom-paristech fr
xgerli02 @ vut cz
jbreier @ jbreier com
anupam @ ntu edu sg
ritu-ranjan shrivastwa @ secure-ic com
martinasek @ vut cz
sbhasin @ ntu edu sg
History
2024-07-01: last of 5 revisions
2024-06-18: received
See all versions
Short URL
https://ia.cr/2024/984
License
Creative Commons Attribution-NonCommercial-ShareAlike
CC BY-NC-SA

BibTeX

@misc{cryptoeprint:2024/984,
      author = {Aneesh Kandi and Anubhab Baksi and Peizhou Gan and Sylvain Guilley and Tomáš Gerlich and Jakub Breier and Anupam Chattopadhyay and Ritu Ranjan Shrivastwa and Zdeněk Martinásek and Shivam Bhasin},
      title = {Side-Channel and Fault Resistant {ASCON} Implementation: A Detailed Hardware Evaluation (Extended Version)},
      howpublished = {Cryptology {ePrint} Archive, Paper 2024/984},
      year = {2024},
      url = {https://eprint.iacr.org/2024/984}
}
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